1. Field of the Invention
The present invention relates to a semiconductor device in which a p-channel MIS transistor and an n-channel MIS transistor are formed on the same substrate, and more particularly, it relates to a semiconductor device with an improved gate electrode structure and a manufacturing method thereof.
2. Description of the Related Art
Recently, in silicon complementary metal insulator semiconductor (CMIS) devices, an attempt has been made to use, as a gate electrode, a refractory metal such as titanium, molybdenum, tungsten or tantalum, or a nitride thereof. This is what is called a metal gate technique.
In the metal gate technique, depletion layers are not generated within the gate electrode in principle, and there is therefore no decrease caused in current drivability of a MIS transistor due to the depletion layers, in contrast with the case of a silicon gate. A TaCx metal gate technique is described in, for example, J. K. Schaeffer et al., “Challenges for the Integration of Metal Gate Electrodes”, 2004 IEDM, p.p. 287 to 309). However, in this document, there is no report on physical property values other than the work function and specific resistance regarding TaCx physical properties.
Furthermore, there is a so-called dual metal gate technique in which a metal gate electrode having the same work function as that of n+ silicon is disposed for an n-channel MIS transistor and a metal gate electrode having the same work function as that of p+ silicon is disposed for a p-channel MIS transistor. In the dual metal gate technique, a threshold voltage can be controlled in the same manner as the conventional silicon gate technique, and it is possible to design a transistor having a low threshold voltage.
However, in the dual metal gate technique, since materials of the gate electrodes in the p-channel MIS transistor and the n-channel MIS transistor are different, film formation for these gate electrodes needs to be separately carried out, so that this technique has a large problem in that the gate electrodes have to be processed independently for the p-channel MIS transistor and the n-channel MIS transistor, in addition to problems such as increased film formation process steps and complication. This dual metal gate technique is most desirable in terms of transistor performance, but the above-mentioned problem of the complication of its manufacturing method has to be solved to achieve this technique.
As has been described, it is essential to replace the conventional silicon gate and introduce the metal gate technique in order to improve the current drivability of the transistor and realize a silicon CMIS device with a high processing speed. The dual metal gate technique is essential for enhanced performance because it can set a low threshold voltage of the transistor, but the complication of its manufacturing method has been the major obstacle to practical application.
It has therefore been desired to achieve a semiconductor device and a manufacturing method thereof capable of realizing a dual metal gate structure whose manufacturing method is easy and contributing to a characteristic improvement of the CMIS devices and the like.